Thin sheet ferrite memory matrix and method



June 19, 1962 G. N. HOWATT ETAL 3,040,301

THIN SHEET FERRITE MEMORY MATRIX AND METHOD Filed March 28, 1957 Z1 14 I 3. U%@9F Mofi WW/W/W/Ms 76 W/rw 00 f /f /f 000/ INVENTORS GLENN N. HOWQ RBRHHAN I. DRQN BY WHLTEI? WELKOW HTTO ENE I United States. Patent 3,040,301 THIN SHEET FERRETE MEMGRY MATRIX AND METHQD Glenn N. Howatt, Abraham 1. Dranetz, and Walter Welkowitz, Metuchen, NJ, assignors to Gnlton In- ;lustries, Inc., Metuchen, N.J., a corporation of New ersey Filed Mar. 28, 1957, Ser. No. 649,244 12 Claims. (Cl. 340-474) Our invention relates to memory matrices and in particular to those matrices which are comprised of ferrites formed in thin sheets and to a method of producing such matrices.

At the present time ferrite memory matrices are made with toroidal ferrite cores. One such core is strung at each intersection of a matrix plane of mutually perpendicular writing conductors. A third sensing conductor, which is also in the'plane of the matrix, makes an angle of substantially 45 with the aforementioned conductors and is also threaded through each core. The construction of matrices of this type is expensive and the space occupied by such a matrix is quite large.

Accordingly, it is a principal object of our invention to provide a ferrite memory matrix which is economical to produce.

It is a further object of our invention to provide such a matrix which contains a large number of'memory cells or units in a relatively small space.

It is a still further object of our invention to provide such a matrix which is rugged.

It is -a still further object of our invention to provide a memory matrix whose operating power requirements are low.

It is a still further object of our invention to provide a method for producing such matrices.

These and other objects, advantages, features and uses will become more apparent as the description proceeds when considered in view of the accompanying drawings,

in which:

FIGURE 1 is a perspective drawing of the presently used ferrite toroid showing the conductors threaded through the toroid,

FIGURE 2 is a plan view of the conductor pattern of the memory matrix of our invention, with the ceramic removed, showing the position of the conductors throughout the matrix as if the body of the matrix were transparent, and

FIGURE 3 is a cross-sectional view along the line 33 of FIGURE 2, somewhat enlarged to show the structural details.

In FIGURE 1, 1t designates a presently used ferrite toroid through which are threaded writing or read-in input Wires 11 and 12 and sensing wire 13. In FIG- URES 2 and 3, wherein, for the purpose of illustration, is shown a preferred embodiment of our invention, 14 designates a memory matrix of our invention, generally. 14 is comprised of ceramic ferrite sheets 15, 16, 17 and 18 to the interfaces of which have been applied conductors 19, 20 and 21.

FIGURE 1 illustrates a conventional toroid core memory cell 10. It is formed of ferrite ceramic or other ferromagnetic material having a suitably square BH loop and is strung at the intersection of two mutual- .ly perpendicular wires 11 and 12. Sensing wire 13 is also threaded through 10. The device is designed so that 10 will not be magnetized by the flow of a current pulse i in 11 or'i in 12 alone but 10 will be magnetized substantially to saturation when there is a coincidence of current pulses i and i in 11 and 12, respectively. Since magnetization is proportional to ampereturns divided by the length of the magnetic paths, and

since there is only one turn of wire linked to each core, the only way to reduce the writing current in a given toroid ferrite material is to make the magnetic path as short as possible. The only way to reduce the magnetic path length is to reduce the diameter of the toroid. Obviously, this diameter cannot be reduced to an extent that makes it impossible for the wires to be threaded through the toroid opening.

We have found that by means of our invention the magnetic path length is reduced to a minimum while also obtaining other advantages. Matrices of our invention are made by forming square loop ferrite ceramic material into thin sheets 15, 16, 17 and 18 in accordance,

with the technique taught by Glenn N. Howatt in his Patent 2,486,410. Sheet 15 has applied thereto ribbonlike strips of conducting layers 19 of platinum, palladium, ceramic paint or similar material on one surface by the conventional silk-screen printing or other suitable method. 16 has strips of conducting layers 21 applied to one of its surfaces in a similar manner and 17 has strips of conducting layers Zil applied-to one of its surfaces in a similar manner. The four-layer sandwich is then assembled so that the outer surfaces are non-conducting and Z1 is located between 19 and 20 as shown in FIG- URES 2 and 3 and the combination is fired to maturity in an oven. The resulting integral body of magnetic material is in the form of a thin plate having three groups of coplanar conductors spaced apart in a direction parallel to the thickness of the plate. Alternatively, it may be more desirable to deposit conducting layers on both surfaces of 16, for example, and on one surface of 17 but the essential result is to have each conducting layer between two layers of ceramic and non-conducting surfaces on the outside of the combination.

We have found that the thin sheet technique of Glenn N. Howatt is far superior to any other method of forming the memory matrices. For example, molding methods tend to produce sheets which are not homogeneous with the result that the magnetic properties are not uniform and the distortion in firing causes strains which distort the conductor patterns. If embedded solid metal wires are used instead of the printed wiring, strains are introduced in the body when the combination is cooled after firing because the metals and the ceramic ferrites have substantially different coefiicients of thermal expansion. I

To illustrate the basic theory underlying our memory matrix by way of example and not by way of limitation, let us assume that all layers are of substantially the same ferrite ceramic material; that the coincident Writing currents i in 19 and i in 20 are equal; that the thickness of the outer layers 15 and 18 are each equal to t and that the thickness of the inner layers 16 and 17 are each equal to t,. We shall further choose to write by coincidence of equal currents each of which alone will not suffice to change the magnetization of the matrix cell.

It follows that the width w of 19' and 20 should be at least such that the minimum path 2w around it is too long to magnetize the surrounding material due to a current z' or i It also follows that the length of the magnetic path around 19 and 20 at their intersection, 2w+4t, must be short enough so that a current 1=i +i passing through the ferrite material in the region of the intersection'will saturate it. In order to make 2w+4t smaller than 4w it is necessary that t, be smaller than w.

In order to minimize the magnetic path lengths, .and thereby the required writing current, inner layers 16 and 17'should be as thin as practicable, say of the order of 0.01", and 19 and 20 should then be wider than 0.01". The thickness of outer layers 15 and 13 is'less critical but if it is too great, the longest magnetic path around 19 and 21' will be much greater than the shortest path I and there will be an undesirable loss in the effective squareness ratio of the B-H loop. This is due to the fact that the domains of the magnetized paths, which are longer, will change polarity only as the magnetizing current increases resulting in a slanting of the vertical region of the B-H loop.

It is desirable that 19 and 20 cross substantially at right angles since if they do not do so, a current in 19 will induce a spurious current pulse in 24) and vice versa. Sensing wire 21 may be of any practical width but it should not be substantially more than 0.7 times the width of 19 or 20, so that it does not obstruct the shortest magnetic path around 19 and 20. 21 should pass through the center of the intersection of 19 and 20. It is within the contemplation of our invention to form three-layer ferrite ceramic sandwiches with two sets of intersecting conducting strips which do not, of necessity, cross at right angles.

It can be seen that the thickness of the ceramic at the conductors intersection defines the performance of each cell. A cell is defined as a memory element located at the intersection of the conductors. It is possible to adjust the performance of individual cells after firing by, for example, grinding off an appropriate amount of ceramic from the outside surface or surfaces of one or more cells while leaving the balance of the cells untreated. Such grinding reduces the magnetic paths cross-section at the area so treated. v

In operation, suitable connections (not shown) are made to the strips of conducting layers 19, 2G and 21, preferably at the edges of the matrix, and they are connected in the conventional manner to external circuitry as required by the particular application in which the matrix is being used.

While we have described our invention by means of specific examples and in specific embodiments, we do not wish to be limited thereto, for obvious modifications will occur to those skilled in the art without departing from the spirit of our invention and the scope of the subjoined claims.

Having thus described our invention, we claim:

1. A memory matrix comprising four layers of ceramic ferrite material, a first plurality of non-intersecting conducting strips extending in generally the same direction at the interface of one of the outer layers with the layer adjacent thereto, a second plurality of non-intersecting conducting strips extending in generally the same direction at the interface of the other outer layer with the layer adjacent thereto, said second plurality of conducting strips being perpendicular to said first plurality of conducting strips, a third plurality of conducting strips at the interface of the two inner layers, said third plurality of conducting strips crossing in the center of each intersection of said first and second plurality of conducting strips.

2. A memory matrix comprising three layers of ceramic ferrite material, a first plurality of non-intersecting conducting strips extending in generally the same direction at the interface of one of the outer layers with the inner layer, a second plurality of conducting strips at the interface of the other outer layer with the inner layer, said second plurality of conducting strips being at an angle to said first plurality of conducting strips so as to form. intersections therewith.

3. A memory matrix comprising a plurality of layers of ceramic ferrite material, a plurality of layers of conducting strips aifixed to said ceramic layers at the interfacesiof said ceramic layers, the strips in each layer of 4 adjacent thereto, a second plurality of conducting strips at the interface of the other outer layer and the layer adjacent thereto, said second plurality of conducting strips being perpendicular to the projection of said first plurality of conducting strips on the plane of said second plurality of conducting strips, a third plurality of conducting strips at the interface of the two inner layers, the projection of said third plurality of conducting strips on the plane of said second plurality of conducting strips making an angle of 45 with said second plurality of conducting strips, said third plurality of conducting strips being placed so that each of the strips in its projection on the plane of said second plurality of strips passes through the intersections of said second plurality of strips and the said projection of said first plurality of strips.

5. A memory matrix as described in claim 4 wherein the Widths of said conducting strips of said first and said second plurality of conducting strips being greater than the thickness of either of said inner ceramic layers.

6. A magnetic core storage matrix comprising: a solid body of non-conductive magnetic material constituting a magnetic storage medium having a number of individual storage regions for information to be stored, said body having therein a first group of substantially parallel, coplanar conductors constituting read-in conductors for the matrix, and a second group of substantially parallel, coplanar conductors constituting sensing conductors, said second group of conductors being in a plane spaced from but parallel to the plane of said first group of conductors and extending in a direction oblique to said first group of parallel conductors to thereby overlap the same at a plurality of points which locate said individual storage regions.

7. A magnetic core storage matrix comprising: a soli body of non-conductive magnetic material constituting a magnetic storage medium having a number of individual storage regions for information to be. stored, said body having embedded therein a first group of substantially parallel, coplanar conductors constituting read-in conductors for the matrix, and a second group of substantially parallel, coplanar conductors embedded in said body and constituting sensing conductors, said second group of conductors being in a plane spaced from but substantially parallel to the plane of said first group of conductors and extending in a direction oblique to said first group of parallel conductors to thereby overlap the same at a plurality of points which locate said individual storage regions.

8. A magnetic core storage matrix comprising: a solid body of non-conductive magnetic material constituting a magnetic storage medium having a number of individual storage regions for information to be stored, said body having a first group of substantially parallel, coplanar conductors embedded therein and constituting read-in conductors for the matrix, a second group of substantially parallel, coplanar conductors embedded in said body and constituting read-in conductors, said second group of conductors being in a plane spaced from but parallel to the plane of said first group of conductors and extending in a direction transverse to said first group of conductors to thereby overlap the same at a plurality of points which locate said individual storage regions, and a third group of substantially parallel, coplanar conductors constituting sensing conductors, said third group of conductors being embedded in said body in spaced parallel relation between said first and second groups of conductors and extending obliquely thereof and crossing the same at said points of overlap thereof.

9. The magnetic core storage matrix of claim 6 wherein said solid body of magnetic material is in the form of a flat plate with said planes extending transverse to the thickness of the plate.

10. The magnetic core. storage matrix of claim. 6 V

wherein said conductors are in the form of thin, flat rib- 5 bons with the flat faces of the ribbons parallel to the planes of the groups of conductors.

11. The magnetic core storage matrix of claim 7 wherein said conductors are in the form of thin, fiat ribbons with the flatfaces of the ribbons parallel to said planes and said first and second group of conductors being spaced apart a distance less than the Widths of said first group of conductors.

12. The magnetic core storage matrix of claim 7 wherein said conductors are in the form of thin, flat ribbons with the fiat faces of the ribbons substantially parallel to said planes, said first and second group of conductors being spaced apart a distance less than the widths of said first group of conductors, and said second group of conductors having a width substantially less than the widths of said first group of conductors.

References Cited in the file of this patent UNITED STATES PATENTS 2,700,150 Wales Jan. 18, 1955 6 2,724,103 I, Ashenhurst Nov. 15, 1955 2,743,507 Kornei May 1, 1956 2,746,130 Davis May 22, 1956 2,911,627 Kilburn'etal. Nov. 3, 1959 2,919,432 Broadbent Dec. 29, 1959 FOREIGN PATENTS 201,561 Australia Apr. 18, 1956 845,604 Great Britain Aug. 24, 1960 OTHER REFERENCES Ferroelectrics for Digital Information Storage and Switching, Dudley A. Buck, Report R-212, Massachusetts Inst. of Tech., June 5, 1952.

Magnetic and Ferro-electric Computing Components, Newhouse, Electronic Engineering, May 1954, pp. 192- 199.

An Analysis of the Operation of a Persistent-Supercurrent Memory Cell, R. L. Garwin. I.B.M. Journal, 1957, pp. 304-308. 

